Design verification is a common process for testing an integrated circuit, board, or system-level architecture, to confirm that it complies with the requirements defined by the specification of the architecture for that device. Design verification for a device under test (DUT) may be performed on the actual device, or on simulated on a simulation model of the device.
Testing a design using a simulation model of the device involves using hardware description languages (HDL) such as Verilog and VHDL. These languages are designed to describe hardware at high levels of abstraction. The generated simulated model of the tested device can receive input stimuli in the form of test vectors, which are a string of binary values applied to the input of a circuit. The simulated model then produces results, which are checked against the expected results for the particular design of the device.
System level test generation typically entails representation of large abstract data models with complex set of rules. Automating the process of creating such data models is often prohibitively expensive in terms of time and computing power. Furthermore, performing the simulated test on the simulation model with numerous test vectors may consume enormous amounts of time and computing power.